1. Field of the Invention
This invention relates to an electrically erasable programmable non-volatile semiconductor memory device, and also to a method of manufacturing the device.
2. Description of the Related Art
Electrically erasable programmable non-volatile semiconductor memory devices include a NAND type EEPROM and a FLOTOX (floating gate tunnel oxide) type EEPROM, which have select transistors, and a NOR type EEPROM with no select transistor. In the EEPROMs with select transistors, the state of each memory cell is determined depending upon whether it has a positive threshold voltage or a negative threshold voltage. Therefore, if there are no select transistors, a cell current will be flown into the non-selected cell, resulting in erroneous operation, where a memory cell having a negative threshold voltage is used as a non-selected cell. To avoid this, select transistors are connected to memory cells in series.
FIG. 1 is a circuit diagram, showing part of a memory cell array employed in the conventional NAND type EEPROM. As is shown in FIG. 1, there are provided lamination type memory cells 191 (hereinafter referred to also as "cells") connected in series and controlled by control gates CG1-CG8. Select transistors 192 are connected to the opposite ends (i.e., the drain side D and the source side S) of the series circuit of the memory cells, respectively, so as to control bit lines BL1 and BL2 with the use of select gates SG1 and SG2. FIG. 2 is a table indicating examples of voltage applied when erasing, writing and reading are performed in a memory cell.
At the time of erasing, a bit line BL and a source S are opened, all the control gates CG are biased to 0 V, and an erasing voltage VEE of, for example, 20 V is applied to a substrate W and select gates SG1 and SG2, thereby drawing electrons from all floating gates by the use of tunnel phenomenon in the oxide film. As a result, the threshold voltages of all the cells are reduced to 0 V or less, in other words, the cells are set in a normally-on state (=a depletion state; a "data 1" state).
At the time of writing, a writing voltage Vpp of, for example, 20 V is applied to the control gate CG of a selected cell, and an intermediate voltage Vm between Vpp and 0 V, for example, 10 V is applied to the control gates CG of a non-selected cell. In this state, 0 V is applied to that one of the bit lines which is connected to the cell in which data "0" is to be written, and Vm is applied to that one of the bit lines which is connected to the cell in which data "1" must be kept.
In the above-described potential state, in the selected cell having its control gate supplied with Vpp and its bit line supplied with 0 V, the voltage Vpp is divided at the ratio (Cs2/(Cs1+Cs2)), hereinafter called a "coupling ratio", of an electrostatic capacitance (Cs2) between the floating gate and the control gate to the sum of an electrostatic capacitance (Cs1) between the floating gate and the semiconductor substrate and the electrostatic capacitance (Cs2). For example, in the case of Cs2/(Cs1+Cs2)=0.5, the potential difference between the floating gate and the semiconductor substrate is 10 V. In this case, the intensity of the electric field applied to the gate oxide film (hereinafter called a "tunnel oxide film") formed between the floating gate and the semiconductor substrate is 10 MV/cm where the tunnel oxide film has a thickness of 10 nm. In this state, a Fowler-Nordheim current (hereinafter called a "tunnel current") flows through the tunnel oxide film, and electrons flow into the floating gate. As a result, the threshold voltage of the cell becomes positive, thus writing data of "0" into the selected cell.
The potential Vm is applied to the control gates of the non-selected cells contained in a NAND ("NAND" indicates a memory cell unit formed by connecting in series the cells which are arranged between the select gates SG1 and SG2) in which the cell (which has, for example, a control gate CG4 and is connected to a bit line BL1) into which data "0" is to be written is included, and in other NANDs connected to the bit line BL1. This is done for turning on the non-selected cell transistors, to apply the bit line potential of 0 V to the channels of the selected cell and provide the selected cell with sufficient writing characteristics. At this time, writing is not performed since the intensity of the electric field applied to the tunnel oxide film of each non-selected cell is about 5 MV/cm. On the other hand, at the time of writing data "1" into a cell (which has, for example, the control gate CG4 and is connected to a bit line BL2) which uses the same control gate as the above-described selected cell, the potential of the bit line BL2 is set to Vm. In this state, no writing is performed and the data of "1" is kept in the cell (CG4, BL2) since substantially Vm is applied to the channel of the cell. The threshold voltage of the cell into which data is to be written is set to a value higher than 0 V and lower than Vcc (e.g. 5 V).
At the time of reading data, a bit line connected to a selected cell is precharged with Vcc (e.g. 5 V), while a bit line connected to a non-selected cell is precharged with 0 V. Further, 0 V is applied to the control gate of the selected cell and Vcc is applied to that of the non-selected cell. In this state, the select transistors (192) are turned on to determine whether the selected cell has data "0" or "1", depending upon whether or not a current flow therein through the bit line. If the cell is in a depletion state, current flows therein, whereas if the cell has a positive threshold voltage, no current flows therein. FIG. 3 shows the electrostatic characteristics of a cell having a threshold voltage higher than 0 V and those of a cell having a threshold voltage lower than 0 V. In FIG. 3, VCG denotes a voltage applied to the control gate of each cell, and Ida drain current thereof.
In general, each memory cell has a sufficiently thin oxide film (tunnel oxide film) of about 10 nm formed between the semiconductor substrate and the charge accumulating region for enabling a tunnel current to flow therein to write or erase data. On the other hand, the gate oxide film of the select transistor must have such a thickness as can prevent a tunnel phenomenon, i.e., as can interrupt a tunnel current, since the transistor must perform a normal operation. If the gate voltage of the select transistor is 10 V during writing, the gate oxide film of the select transistor (SG) must have a thickness of about 30 nm.
An explanation will be given of the steps of manufacturing a semiconductor device in which the gate oxide film of a memory cell has a thickness differing from that of a select transistor.
FIG. 4 is a plan view, showing part of a memory cell array employed in the conventional NAND type EEPROM. FIGS. 5A-5J, FIGS. 6A-6J, FIGS. 7A-7C and FIGS. 8A-8C are views, taken along lines 5--5, 6--6, 7--7 and 8--8 of FIG. 4, respectively.
As is shown in FIGS. 5A and 6A, element-isolating regions 102 are selectively formed in the surface of a semiconductor substrate 101 (FIG. 6A). Then, as is shown in FIGS. 5B and 6B, a first gate oxide film 103 with a thickness of 25 nm is formed on the substrate 101 by thermal oxidation. As is shown in FIGS. 5C and 6C, that part of the first gate oxide film 103 which is located on a memory cell region 104 is removed by photolithography or wet etching (e.g. using NH.sub.4 F). Subsequently, as is shown in FIGS. 5D and 6D, a second gate oxide film 105 with a thickness of 10 nm is formed by thermal oxidation.
In general, a photosensitive material (resist) used in photolithography contains a metal impurity, which may degrade the quality of the gate oxide films. Forming gate oxide films of different thicknesses without degrading the quality thereof inevitably increases the number of manufacturing steps and makes the manufacturing more complicated.
Thereafter, as is shown in FIGS. 5E and 6E, a first polysilicon film 106 with a thickness of 200 nm is deposited on the gate oxide films 103 and 105. The film 106 is doped with 1.times.10.sup.20 cm.sup.-3 of P or As. The density of the impurity is set relatively low so as to minimize a reduction in the breakdown voltage of the gate oxide film 105, which may be caused by the diffusion of a dopant in a heating step performed later. Then, as is shown in FIGS. 5F and 6F, the polysilicon film 106 is worked with the use of photolithography and aeolotropic etching, thereby forming a floating gate and floating gate-isolating regions 107 (FIG. 6F). Subsequently, as is shown in FIGS. 5G and 6G, an insulating film 108 with a thickness of, for example, 25 nm, which consists of a silicon oxide film or a lamination film (ONO film) of a silicon oxide film and a silicon nitride film, is formed on the first polysilicon film 106 and the floating gate-isolating regions 107. Thereafter, as is shown in FIGS. 5H and 6H, a second polysilicon film 109 with a thickness of, for example, 400 nm is deposited on the first polysilicon film 108, and is then doped with 5.times.10.sup.20 cm.sup.-3 of P or As. Then, as is shown in FIGS. 5I and 6I, the resultant structure is worked by photolithography and aeolotropic etching, thereby simultaneously forming a select transistor portion 110 and a memory cell portion 111 (FIG. 5I).
As is shown in FIGS. 7A and 8A, that part of the second polysilicon film 109 is removed, which constitutes part of the gate electrode 112 of the select transistor. In other words, FIG. 8A shows a process for forming a contact portion of each of select gates arranged, for example, at every 128th or 256th bit lines, to facilitate signal transmission. FIG. 7A shows a process for forming a contact portion to be connected to a decoder. Then, as is shown in FIGS. 7B and 8B, an interlayer insulating film 113 such as BPSG (Boron Phospho-Silicate Glass) is deposited on the resultant structure. Reference numeral 116 denotes an oxide film formed before the deposition of the insulating film 113. As is shown in FIGS. 7C and 8C, contact holes 114 are formed, by means of photolithography and aeolotropic etching, in that portions of the insulating film 113 which are located on the first and second polysilicon films of the select transistor (and also on a memory cell, and drain and source regions, which are not shown). Subsequently, an aluminum wire 115 (i.e., a bit line BIT) is formed to connect the first polysilicon films 106 and 109 of the select transistor to each other.
To connect the first and second polysilicon films 106 and 109 of the select transistor is based on the following grounds:
Although the first polysilicon film 106 functions as the gate electrode of the select transistor, it has a high resistance. This is because a great amount of impurity cannot be introduced into the first polysilicon film which contacts the tunnel oxide film, to prevent the breakdown voltage of the tunnel oxide film from being reduced. Accordingly, the polysilicon film 106 cannot be effectively used as a wire, and instead the polysilicon film 109 formed thereon is used as a wire.
On the above-described grounds, contact holes must be formed in both the first and second polysilicon films 106 and 109, which means that a large number of contact holes must be formed. A large number of contact holes require contact fringes as mask tolerance. Accordingly, the larger the number of contact holes, the lower the integration of elements. Such select gates must be arranged, for example, at every 128th or 256th bit lines, which makes it difficult to increase the degree of integration of elements.
Moreover, as is shown in FIG. 5E, the second gate oxide film 105, which is thin enough to flow a tunnel current therethrough for writing or erasing data, is formed in the memory cell region 104. On the other hand, the select transistor requires the first gate oxide film 103, which has such a thickness as enables a normal transistor operation, in other words, such a thickness as can prevent a tunnel phenomenon (i.e. can prevent a tunnel current from flowing therethrough). To form oxide films of different thicknesses, mask tolerance is necessary in the process of photolithography, that is, tolerance is necessary for alignment between the boundary of the gate oxide film and the tunnel oxide film of the select transistor, and the gate electrode end of the memory cell or of the select transistor. The mask tolerance inevitably reduces the degree of integration of elements.